1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor-mounting heat-radiative substrates in which a plurality of CuW or CuMo composite metal alloys having different compositions are joined together with Cu interposed therebetween and further relates to semiconductor packages using the substrates.
2. Description of the Prior Art
In the last few years, an increase in operating speed and degree of integration of ICs, transistors and the like as well as an increase in their capacity has involved increasing amounts of heat generated by semiconductor devices. As a result of this, it matters to a great extent how generated heat is eliminated and the devices are cooled to accomplish successful operation thereof. In terms of cooling devices, there is a similar problem also in parts related to semiconductor lasers. In order to solve this problem, composite materials formed of combinations of Cu and W, or Cu and Mo have recently come into practical use as heat-radiative substrates for mounting devices in packages in which semiconductors are accommodated.
These composite materials are manufactured by some methods, for example, (a) in which Cu melted in a reducing atmosphere is infiltrated into a porous product obtained by sintering W or Mo powder (as disclosed in Japanese Patent Laid-Open Publication No. 59-21032), and (b) in which W or Mo powder is mixed with Cu powder and moreover the result is sintered in a reducing atmosphere (hereinafter, referred to as mixed powder sintering method).
FIGS. 7 and 8 are sectional views showing typical constructions of conventional IC ceramic packages in which the above-described composite materials are used as heat-radiative substrates; and FIGS. 9 and 10 are sectional views showing constructions of such packages for use with transistors.
In FIGS. 7 and 8, designations are as follows: 21 denotes a substrate composed of CuW or CuMo; 22 denotes a multi-laminated ceramic substrate composed of, for example, Al.sub.2 O.sub.3 layers; 23 denotes an Si semiconductor device mounted on the substrate 21; 24 denotes a covar (Fe--29%Ni--17%Co) lead wire; 25 denotes a bonding wire; and 26 denotes a package composed of covar or Al.sub.2 O.sub.3.
The construction shown in FIG. 8 is such that the Si semiconductor device 23 mounting portion 21a of the substrate 21 is higher than the construction in FIG. 7. Accordingly, the terminal mounting portion 27 of the multi-laminated ceramic substrate 22 can be flush with the Si semiconductor device 23, thus advantageous for mounting devices.
The number of laminates of ceramic substrates is recently increasing with increasing capacity of ICs: the demand for such constructions is therefore increasing more and more.
Conventional transistor-oriented packages are now described, referring to FIGS. 9 and 10. In FIG. 9, on a BeO circuit substrate 28 in the center of a CuW or CuMo substrate 21 there is mounted an Si semiconductor device 23. In FIG. 10, on the other hand, as is the usual case for use with FETs (Field Effect Transistors) employing GaAs transistors as devices 29, a GaAs transistor device 29 is directly mounted to a protrusive portion 21b provided on a CuW or CuMo heat-radiative substrate 21 having a good heat conductivity and the device can be wired with a circuit 31 provided on an insulating ceramic substrate 30 in the vicinity of the device so as to be flush with the circuit, which type of construction is thus preferred.
The substrates 21 used in the packages shown in FIG. 7 and FIG. 9 out of the above-described ones are simple flat plates which do not involve much difficulty in manufacture thereof, whereas the stepped substrates partly having protrusions 21a and 21b as shown in FIG. 8 and FIG. 10 involve various problems on manufacture thereof.
These stepped substrates are manufactured, in general, by leaving protrusive portions on a sheet of flat plate and removing the remains thereof by cutting or grinding.
This method, however, is wasteful in material to be cut and, what is more, burdened with cost for cutting tools due to the fact that its substrate material is of combination of Cu, which is a soft material, and W or Mo, which is a hard, difficult-to-cut material, and therefore the cutting tools are unavoidably subject to intermittent cutting, with the result of their greatly worn edges, which requires cutting tools to be frequently exchanged to obtain high precision and suppress any after-processing machining distortions.
On the other hand, it is possible to provide these stepped substrates by taking the above-described methods, that is, by the infiltration method (a) that Cu is infiltrated into a stepped, sintered product of W or Mo or by the mixed powder sintering method (b) that mixed powder of W or Mo and Cu is molded into a stepped shape and then sintered. However, these methods are accompanied by the following problems.
The substrate 21 used for a package having such a configuration as shown in FIG. 8 is shaped as shown in FIG. 11, where the surface 33 brazed to the ceramic substrate 22 is larger in area than the surface 32 on which the semiconductor device 23 is mounted. The surface 33 is often required to be as thin as 0.3 to 0.5 mm, normally.
Accordingly, in manufacturing such substrates by cutting off a flat plate so as to leave a protrusive portion thereof, the area of the part to be cut off is large and, when the edge of the cutting tool is worn, the mounting surface 33 is deformed due to machining distortion in cutting, thus often encountering an obstacle in brazing it with the ceramic substrate 22.
Some other methods may be available to manufacture these substrates. For example, one method is that W or Mo powder is molded by die-pressing into a stepped shape similar to the foregoing one and Cu is infiltrated into a porous product obtained by sintering the molding result (the infiltration method). Another is that mixed powder of W or Mo powder and Cu powder is molded by die-pressing into a stepped shape similar to the foregoing one and the result is sintered (the mixed powder sintering method). However, as described above, in the shape of FIG. 11, the surface 33 to be brazed with the ceramic substrate 22 is thin such that a die-pressing result having the same density as the semiconductor-device mounting surface 32 is difficult to obtain. Moreover, even if a die-pressing result having the same density is obtained, the brazed surface 33, which forms the thin-wall portion of the die-pressing result, is low in strength, thus difficult to treat.
In addition, in order to obtain composite materials having no defects (empty holes). high-temperature treatment over the melting temperature of Cu is necessitated as the baking temperature. In order to fill empty holes sufficiently with Cu, excessive Cu needs to be added for baking, which causes the baking result to be covered in its surface with Cu. Accordingly, some countermeasure must be taken to remove the resulting Cu, requiring labor equivalent to that in manufacturing the substrates from flat plates by cutting.
Next, the heat-radiative substrate 21 used for transistor-oriented packages, having a sectional configuration as shown in FIG. 10, is shaped as shown in FIG. 12, where the protrusive portion 21b on which the GaAs transistor device 29 is mounted is much smaller than the flat portion 34.
Therefore, it is difficult to manufacture a die for press-forming such a protrusive portion and to charge powder into the die for die-pressing, involving some problems in manufacturing.
As a method for manufacturing such a stepped substrate, such one is available that the protrusive portion and the flat portion are separately prepared, subjected to Ni plating (to ensure the wetting of brazed material in brazing), and brazed along with the ceramic portion in manufacturing ceramic packages to obtain packages such as shown in FIG. 13. However, in this case, it is difficult to take a constant interval of a semiconductor-device mounting substrate 35 to a ceramic portion 36, and moreover, due to empty holes remaining within a brazing material 37 which is the joint surface between the substrates 35 and 36 and due to the intervening brazing material 37 having a low heat conductivity, heat conduction will adversely be affected. This will cause quality deviations of packages, disadvantageously.